For the design of digital circuits (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL (Very high-speed integrated circuit HDL) and Verilog HDL, have evolved as industry standards. VHDL and Verilog HDL are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL), or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the HDL source code describes the circuit elements, and a synthesis process produces an RTL netlist from this source code. The RTL netlist is typically a technology independent netlist, in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist which can be used to create circuits in the vendor's technology/architecture. Field Programmable Gate Array (FPGA) vendors use different technologies and architectures to implement logic circuits within their integrated circuits. This results in a final netlist which is specific to a particular vendor's technology and architecture.
High Level Synthesis (HLS) is a process of converting the behavioral descriptions of HLD (High Level Description) to register transfer level (RTL) descriptions. HLS is typically done with a set of design goals and constraints. So while there may be many different ways to implement the behavior of the HLD, HLS seeks to do so while minimizing particular defined costs. The defined costs are typically things such as cycle time, part count, silicon area, power, interconnections, pin count, etc. The constraints are typically driven by form factors, packaging constraints, interoperability and similar concerns. HLS can be described as compiling a specification written in a high level language (HLL), allocating hardware resources to the operations in the specification and then generating the RTL description.
To generate the RTL description, the HLS schedules the operations, allocates the operation to particular functional hardware units, allocates any variables to storage elements, and allocates any data transfers to communications buses that connect the functional units to storage registers and input/output interfaces. In many devices, including Digital Signal Processors (DSP) the RTL description provides inputs and outputs of the system and the algorithms that are to be performed. These are described as frames. Frame based algorithms are described by using frame data. The input data is received in frames and the output data is produced in frames.
Frame based algorithms are typically synthesized in HLS as follows: First the device collects the frame data from an input stream; then the device processes the frame data; and finally the device sends the output frame as an output stream. The frame synthesis includes scheduling of the operations and binding the operations to hardware to obtain an optimized device design. This methodology suffers from low throughput.
Ant Colony Optimization (ACO) is a recent optimization method that has been applied to many different problems. In ACO, each ant constructs a candidate solution and leaves pheromones according to the cost associated with each solution it constructs. ACO allows several different solutions to be found. These can then be compared to each other to find an optimum solution. ACO, however, has distinct limitations that prevent it from being directly applied to existing solution methodologies.